Error correction for fault-tolerant computing: making practical quantum a reality

Gate-based quantum computers are expected to revolutionize research in a wide range of fields including quantum chemistry and complex financial systems, as they will offer significantly higher calculation performance than current classical computers.

Logical qubits, which consist of multiple physical qubits play a major key role in quantum error correction technology, and ultimately the realization of practical quantum computers that can provide fault-tolerant results.

Within conventional quantum computing architectures, calculations are performed using a combination of four error-corrected universal quantum gates (5) (CNOT, H, S, and T gate). Within these architectures, especially quantum error correction for T-gates requires a large number of physical qubits, and rotation of the state vector in the quantum calculation requires repeated logical T-gate operations for approximately fifty times on average. Thus, the realization of a genuine fault-tolerant quantum computer is estimated to require more than one million physical qubits in total.

For this reason, quantum computers in the early FTQC era using conventional architecture for quantum error correction can only conduct calculations on a very limited scale below that of classical computers, as they work with a maximum of about 10,000 physical qubits, a number far below that required for genuine, fault-tolerant quantum computing.

To address these issues, Fujitsu and Osaka University developed a new, highly efficient analog rotation quantum computing architecture that is able to significantly reduce the number of physical qubits required for quantum error correction, and enable even quantum computers with 10,000 physical qubits to perform better than current classical computers, accelerating progress toward the realization of genuine, fault-tolerant quantum computing.

Fujitsu and Osaka University have been promoting joint R&D in quantum error correction technology including new quantum computation architectures for the early FTQC era at the “Fujitsu Quantum Computing Joint Research Division,” a collaborative research effort of the QIQB, established on October 1, 2021 at the campus of Osaka University as part of Fujitsu’s “Fujitsu Small Research Laboratory” program (6).

About the newly developed quantum computing architecture

By redefining the universal quantum gate set, Fujitsu and Osaka University succeeded in implementing a phase rotating gate – a world first– which enables highly efficient phase rotation, a process which previously required a high number of physical qubits and quantum gate operations.

In contrast to conventional architectures that required repeated logical T-gate operations using a large number of physical qubits, gate operation within the new architecture is performed by phase rotating directly to any specified angle.

In this way, the two parties succeeded in reducing the number of qubits required for quantum error correction to around 10% of existing technologies, and the number of gate operations required for arbitrary rotation to approx. 5% of conventional architectures. In addition, Fujitsu and Osaka University suppressed quantum error probability in physical qubits to about 13%, thus achieving highly accurate calculations.

The newly developed computing architecture lays the foundation for the construction of a quantum computer with 10,000 physical qubits and 64 logical qubits, which corresponds to computing performance of approximately 100,000 times that of the peak performance of conventional high performance computers.

Figure: Image of the newly developed quantum computing architecture

Credit: © 2023 Osaka University & Fujitsu Limited

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